1. Field of the Invention
The present invention relates to a digital to analog converter that lightens the load of control imposed on an external device such as a Microprocessor in digital audio equipment or the like.
2. Description of the Related Art
FIG. 8 is a block diagram indicating the configuration of a digital audio apparatus using a conventional delta-sigma digital to analog converter (hereinafter referred to as a Δ ΣDAC). In this figure, reference numeral 101 denotes an audio source such as a CD, MD or DVD. Reference numeral 102 denotes audio input means including a digital signal processor (hereinafter referred to as a DSP), a digital audio interface receiver (hereinafter referred to as a DIR), and an AD converter (hereinafter referred to as an ADC). Reference numeral 103 denotes a Δ ΣDAC, reference numeral 104 denotes audio output means, reference numeral 105 denotes an analog low pass filter, reference numeral 106 denotes a power driver and reference numeral 107 denotes an LC low pass filter.
The operation will then be described.
In the digital audio apparatus shown in FIG. 8, the audio input means 102 reads data recorded on the audio source, generates a Pulse Code Modulation (hereinafter referred to as PCM) type digital audio signal from the data and outputs the signal to the delta sigma DAC 103. The delta sigma DAC 103 converts the incoming PCM type digital audio signal into a Pulse Width Modulation (hereinafter referred to as PWM) type pulse signal and outputs the signal to the audio output means 104. To output an analog audio signal to the corresponding analog audio line, the audio output means 104 has the received PWM type pulse signal go through the analog low pass filter 105. In addition, to drive a speaker for acoustic output, the audio output means 104 inputs the received PWM type pulse signal to the power driver 106 which amplifies the voltage level of the pulse signal to generate a power output signal via the low pass filter 107.
FIG. 9 is a block diagram of a conventional Δ Σ type DA converter. In the figure, reference numeral 103 denotes a delta sigma DAC, reference numeral 110 denotes an audio interface receiving data (referred to as DATA in the figure), a bit clock BCK, and an input sampling clock LRCK, which are acquired from the audio source 101, reference numeral 111 denotes an oversampling digital filter, reference numeral 112 denotes a sampling rate converter, reference numeral 113 denotes Δ Σ conversion means, reference numeral 114 denotes PWM conversion means, reference numeral 115 denotes a Microprocessor interface which receives control signals from external control means such as a Microprocessor equipped outside the delta sigma DAC 103, reference numeral 116 denotes an input side master clock synchronization unit, and reference numeral 117 denotes an output master clock synchronization unit. The input side master clock synchronization unit 116 is provided with the audio interface 110 and the oversampling digital filter 111, both of which operate in synchronization with an input side master clock xfsi. The output side master clock synchronization unit 117 is provided with the delta sigma conversion means 113 and the PWM conversion means 114, both of which operate in synchronization with an output side master clock xfso. The sampling rate converter 112 has its former stage operate in synchronization with the input side master clock xfsi and its latter stage operates in synchronization with the output side master clock xfso. The sampling rate converter 112 is configured so as to belong to both the input side master clock synchronization unit 116 and output side master clock synchronization unit 117.
The operation will next be described.
An audio signal output from the audio input means 102 as PCM type data is taken into the Δ ΣDAC 103 via the audio interface 110. The oversampling digital filter 111 receives audio signal data from the audio interface 110 and perform reflection-preventive low pass filtering operations of the data and oversamples the data based on the input sampling frequency fs. The oversampling digital filter 111 shown in FIG. 9 is configured so as to perform oversampling at a frequency either two, four or eight times higher than the input sampling frequency fs.
The sampling rate converter 112 improves the S/N ratio of the output of the ΔΣ DAC 103 by removing jitter from the clock signal used in generating the PWM type pulse signal. The input side master clock xfsi to be synchronized with the audio signal data is usually generated by a phase lock loop circuit (hereinafter referred to as a PLL) synchronized with the input sampling frequency fs although the PLL is not shown in the figure. However, since suppressing the accompanying jitter by the PLL is limited, the jitter is transmitted to the PWM type pulse signal outputted by the ΔΣ DAC 103, which causes a critical deterioration in the S/N ratio of the DAC output. Thus while the former stage of the sampling rate converter 112 operates in synchronization with the input side master clock xfsi, the latter stage of the sampling rate converter 112 is designed to operate in synchronization with a high accuracy clock generated using a quartz oscillator (not shown in the figure) asynchronous with the input side master clock xfsi. The output of the PWM pulse signal is maintained highly accurate by interrupting the propagation of jitter in this manner.
In the ΔΣ conversion means 113, the data output from the sampling rate converter is quantized into a small number of bits while the quantization noise is given a differential characteristic or higher frequency band enhancement (noise shaping). In the PWM conversion means 114, the data consisting of a small number of bits from the ΔΣ conversion means 113 is converted into a 1-bit PWM pulse signal whose pulse width varies. The 1-bit PWM pulse signal can be converted into an analog signal only by allowing the signal to go through a low pass filter such as the analog low pass filter 105 or the LC low pass filter 107.
Here, the operation of the oversampling digital filter 111 will be described in detail. The oversampling digital filter 111 shown in FIG. 9 performs eight-time-oversampling when it receives, for example, 1 fs (32 kHz to 48 kHz) of a digital audio signal, namely, data of inputted sampling frequency fs; the filter 111 performs four-time-oversampling when it receives 2 fs (64 kHz to 96 kHz); and the filter 111 performs two-time-oversampling when it receives 4 fs (128 kHz to 192 kHz). In this manner, the oversampling digital filter 111 oversamples the audio signal data always at a fixed frequency of 8 fs.
Switching the oversampling operation according to the input sampling frequency fs is performed under control of external control means such as a Microprocessor located outside the ΔΣ DAC 113. The external control means must control the delta sigma DAC 113 so as to change the oversampling frequency depending on the selected audio source 101 such as a CD, MD, or DVD. If there are a plurality of audio input means 102 each incorporating a DSP, DIR, and ADC, the external control means is also in charge of allowing the ΔΣ DAC 103 to selectively receive a signal from the plurality of audio input means 102 to acquire the input sampling frequency fs. In addition, it is necessary to provide mute processing to prevent abnormal sound from being introduced into the audio signal data when the audio source 101 is switched.
FIG. 10 is a block diagram of a conventional ΔΣ DAC having another configuration. Like or corresponding parts of the ΔΣ DAC 103 in FIG. 9 are denoted by the same reference numeral as in FIG. 9 and the explanation thereof is omitted. The ΔΣ DAC 103 in FIG. 10 is different from the ΔΣ DAC 103 in FIG. 9 in that the sampling rate converter 112 is not included. Although a second PLL is provided to suppress the jitter of the master clock xfs in this configuration, it is virtually impossible to raise the performance by suppressing the jitter to the same level as the ΔΣ DAC 103 shown in FIG. 9 where the output side master clock xfso is generated from a quartz oscillator independent of the input side master clock xfsi. In addition, control by external control means such as a Microprocessor to adapt the operation to the input sampling frequency fs which changes depending on each selected audio source 101 is also necessary for the ΔΣ DAC 103 in FIG. 10.
FIG. 11 is a block diagram of a conventional ΔΣ DAC having yet another configuration. Like or corresponding parts of the ΔΣ DAC 103 in FIG. 9 are denoted by the same reference numerals as in FIG. 9 and the explanation thereof is omitted. The ΔΣ DAC 103 shown in FIG. 11 is configured in such a manner that the ratio of the oversampling frequency to the input sampling frequency fs is fixed. This configuration can release the external control means from some burdens of input sampling frequency-dependent control. However, to support a high input sampling frequency in this configuration, it is necessary to simply raise the frequency of the master clock xfs for operational synchronization and therefore raise the operation speed of the ΔΣ DAC 103. However, configuring a high speed ΔΣ DAC is not easy because it is necessary to overcome such problems as spurious radiation and high power consumption due to high speed switching, and followability to high speed switching pulses by the analog low pass filter 105, the power driver 106 and others governing the output operation of the ΔΣ DAC 103.
As described above, however, the conventional ΔΣ DAC have problems if the audio source is switched, an external control means, such as a Microprocessor, must acquire the input sampling frequency associated with the new audio source and adapt the operation of the ΔΣ DAC to the input sampling frequency, and while the audio source is being switched, the external control means must provide mute control to the ΔΣ DAC.